Phil Mulholland

Feb 18

Coding in C for MCUs: Sort Structs to Save Code Size

Exploring the Impact of Hardware Architecture on Code This post explores two things. Firstly, a handy way to save code size on ARM Cortex-M-based MCUs with limited resources. Secondly, it looks at the impact of the hardware architecture on meeting software requirements. In particular, it looks at memory rows and alignment. An Easy Code Size Optimization I’d like to share a simple coding…

5 min read

Coding in C for MCUs: Sort Structs to Save Code Size

Aug 19, 2021

Things to Think About When Doing Low-Level Embedded Systems Development.

What are the foundations of designing and implementing low-level software that interacts with real-world systems? (By low level I mean software running on bare-metal or a small footprint RTOS, on a small processor core — Not embedded Linux on a Cortex-A class MCU) An introductory embedded systems book will often…

Embedded Systems

7 min read

Jun 25, 2021

RISC-V: A Baremetal Introduction using C++. Conclusion.

This is the last post in the series. Is it possible to write pure modern C++ bare-metal firmware from the ground up for RISC-V? The answer is a qualified yes. The toolchain using Platform IO supported modern C++ with a small configuration change. The startup code required some assembly, but…

Cpp

3 min read

RISC-V: A Baremetal Introduction using C++. Conclusion.

Jun 13, 2021

RISC-V: A Baremetal Introduction using C++. Interrupt Handling.

This is the seventh post in a series. This post is about RISC-V interrupt handling in C++. What are the basics of interrupt handing in RISC-V? Can we utilize modern C++ to simplify interrupt handling? RISC-V Machine Mode Interrupts The RISC-V ISA is not specialized for embedded applications (when compared to an ISA such…

Cplusplus

5 min read

RISC-V: A Baremetal Introduction using C++. Interrupt Handling.

Jun 7, 2021

RISC-V: A Bare-metal Introduction using C++. Machine Mode Timer.

This is the sixth post in a series, about the RISC-V machine mode timer and timing keeping using the C++ std::chrono library. How does RISC-V keep time? How can we perform a periodic task with no operating system? You may take for granted that you can simply ask the operating…

Risc V

4 min read

Jun 7, 2021

RISC-V: A Baremetal Introduction using C++. System Registers.

This is the fifth post in a series. What are system registers in RISC-V? How can we access them with modern C++? System registers require special instructions to access, so unlike memory-mapped registers (MMIO) we can’t just cast a pointer to memory to get access them in C++. Do we…

Risc V

4 min read

May 29, 2021

RISC-V: A Baremetal Introduction using C++. Startup.

In the last post, we set up the development environment. This post is about how the RISC-V core executes our program. How do we go from reset to entering the main() function in C++ in RISC-V? …

Risc V

4 min read

May 23, 2021

RISC-V: A Baremetal Introduction using C++. Development Environment

Following on from Part 2, how do we compile this project and run it? For this series of posts, my platform is a SiFive HiFive1 Rev B development board. It’s equipped with a 320MHz RV32IMAC (FE310 core). …

Risc V

4 min read

May 23, 2021

RISC-V: A Baremetal Introduction using C++. Overview.

As described in Part 1, a simple C++ application to blink an LED, what does this look like with no operating system? Blinky in C++ Here we have blinky on SiFive HiFive1 Rev B development board, built and loaded via Platform IO. Let’s look at the program flow, and the C++ and RISC-V…

Risc V

5 min read

May 22, 2021

“RISC-V: A Baremetal Introduction using C++. Intro.

What does it look like to program with no operating system? Can we have direct access to hardware using a high-level language like C++? How does RISC-V work at the most stripped-back bare metal level? This is a series of posts where I’d like to combine those topics for embedded…

Risc V

4 min read