RISC-V: A Baremetal Introduction using C++. Development Environment

Setup

  • -nostartfiles is used as this example includes a custom startup routine,
  • -std=c++17 for all the needed modern C++ features, and
  • -fno-threadsafe-statics to prevent threadsafe code from being emitted (we have no threads and these ensure static declarations are initialized only once).
build_flags = 
-std=c++17
-O2
-g
-Wall
-ffunction-sections
-fno-exceptions
-fno-rtti
-fno-nonansi-builtins
-fno-use-cxa-atexit
-fno-threadsafe-statics
-nostartfiles
-Wl,-Map,blinky.map

Adding a Post Compile Action

extra_scripts = post_build.py
targets = disasm
def after_build(source, target, env): 
""" Run objdump on the target elf file and save the
output in the top dir.
"""
objdump=env.subst("${OBJCOPY}").replace("objcopy","objdump")
src_elf=env.subst("${BUILD_DIR}/${PROGNAME}.elf")
cmd=" ".join([
objdump, "-SC","--file-start-context", "-w",
src_elf,">","${PROGNAME}.disasm"]) #
env.Execute(cmd)
Import("env")env.AddCustomTarget(
"disasm",
"${BUILD_DIR}/${PROGNAME}.elf",
after_build,
title="Disasm 2",
description="Generate a disassembly file on demand",
always_build=True
)

Other C++ Development Environments

  • SiFive, like most processor vendors, has a GCC and Eclipse-based IDE, the Freedom Studio.
  • For a vendor-independent path GNU MCU Eclipse supports RISC-V compilation and debugging very well. I have personally used this to target proprietary RISC-V cores and simulators with success.

Other RISC-V Devices

  • Professionally my experience has been with IQonIC Works RISC-V IP. They provide a small RV32EC core targeted at deeply embedded applications, where stripped-down bare-metal programming is essential.
  • Many open-source options.

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Phil Mulholland

Phil Mulholland

Experienced in Distributed Systems, Event-Driven Systems, Firmware for SoC/MCU, Systems Simulation, Network Monitoring and Analysis, Automated Testing and RTL.