• The toolchain using Platform IO supported modern C++ with a small configuration change.
  • The startup code required some assembly, but was mostly was very readable C++.
  • Drivers accessed via MMIO could be completely abstracted — or wrapped to simply provide convenient access to hardware registers.
  • We could specify system clock delays in human-readable units with zero run time cost.
  • Access to special system registers could be abstracted, and I propose…

RISC-V Machine Mode Interrupts

The Machine Level ISA Timer

RISC-V Special Instructions and C++

auto this_cause = riscv::csrs.mcause.read();

Booting a RISC-V Core

From here https://commons.wikimedia.org/wiki/File:Linux_boot_screen_compact.png
From here https://commons.wikimedia.org/wiki/File:Linux_boot_screen_compact.png
Booting an OS is much more complex, but the entry point relies on the same principles.


Blinky in C++

  • RISC-V has a standard timer. However, there is no standard RISC-V GPIO. On this device, we use SiFive’s GPIO.
  • The C++ drivers are…


Phil Mulholland

Software Engineer, Software Architect, Embedded Systems, Distributed Systems, Digital Design, ソフトウェアエンジニア http://www.linkedin.com/in/phil-mulholland-884a8

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